A. Field of the Invention
This invention relates to FET semiconductors and more particularly to a process and structure for a self-aligned MESFET having reduced series resistance.
B. Description of the Prior Art
Although MESFET's have high device gain relative to MOSFET's and do not require a thin gate oxide which limits the ultimate advancement of MOS devices, MESFET devices have been relatively unnoticed in the past as a result of their large series source and drain resistances which tend to degrade the actual device gain more severely than MOSFET devices. MESFET structures would only become attractive if the series resistance could be reduced by advanced photolithographic techniques which have not been well developed for practical use. Therefore, it is highly desirable to devise means to minimize these undesirable resistances in MESFET structures without requiring advanced photolithographic techniques to thus make MESFET's competitive with MOSFET's.